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DEVICE SPECIFICATION
SONET/SDH/ATM OC-48 16:1 TRANSMITTER BiCMOS LVPECL OC-48 TRANSMITTER AND CLOCK GENERATOR SONET/SDH/ATM OC-12 16:1 TRANSMITTER RECEIVER GENERAL DESCRIPTION
S3043 S3043 S3043
FEATURES
* Micro-power Bipolar supply * Complies with Bellcore, and ITU-T specifications * On-chip high-frequency PLL for clock generation * Supports 2.488 Gbps (OC-48) * Reference frequency of 155.52 MHz * Interface to both LVPECL and LVTTL logic * 16-bit LVPECL data path * Compact 80 PQFP/TEP package * Diagnostic loopback mode * Line loopback * Lock detect * Low jitter LVPECL interface * Single 3.3 V supply
The S3043 SONET/SDH MUX chip is a fully integrated serialization SONET OC-48 (2.488 Gbps) interface device. The chip performs all necessary parallel-to-serial functions in conformance with SONET/SDH transmission standards. The device is suitable for SONETbased ATM applications. Figure 1 shows a typical network application. On-chip clock synthesis PLL components are contained in the S3043 MUX chip allowing the use of a slower external transmit clock reference. The chip can be used with a 155.52 MHz reference clock, in support of existing system clocking schemes. The low jitter LVPECL interface guarantees compliance with the bit-error rate requirements of the Bellcore, and ITU-T standards. The S3043 is packaged in an 80 PQFP/TEP, offering designers a small package outline.
APPLICATIONS
* * * * * * * * * SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment ATM over SONET/SDH Section repeaters Add Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
Figure 1. System Block Diagram
Network Interface Processor
16
S3043 Tx S3044 Rx
OTX
ORX
S3040
S3044 Rx S3043 Tx
16
16
16
S3040
ORX
OTX
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Network Interface Processor
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S3043 SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard for connecting one fiber system to another at the optical level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for fiber interconnect between telephone networks of different countries. SONET is capable of accommodating a variety of transmission rates and applications. The SONET standard is a layered protocol with four separate layers defined. These are: * Photonic * Section * Line * Path Figure 2 shows the layers and their functions. Each of the layers has overhead bandwidth dedicated to administration and maintenance. The photonic layer simply handles the conversion from electrical to optical and back with no overhead. It is responsible for transmitting the electrical signals in optical form over the physical media. The section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. Key functions of this layer are framing, scrambling, and error monitoring. The line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. Its main functions are synchronization, multiplexing, and reliable transport. The path layer is responsible for the actual transport of services at the appropriate signaling rates. Data Rates and Signal Hierarchy Table 1 contains the data rates and signal designations of the SONET hierarchy. The lowest level is the basic SONET signal referred to as the synchronous transport signal level-1 (STS-1). An STS-N signal is made up of N byte-interleaved STS-1 signals. The optical counter-
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
part of each STS-N signal is an optical carrier level-N signal (OC-N). The S3043 chip supports the OC-48 rate (2.488 Gbps). Frame and Byte Boundary Detection The SONET/SDH fundamental frame format for STS-48 consists of 144 transport overhead bytes followed by Synchronous Payload Envelope (SPE) bytes. This pattern of 144 overhead and 4176 SPE bytes is repeated nine times in each frame. Frame and byte boundaries are detected using the A1 and A2 bytes found in the transport overhead. (See Figure 3.) For more details on SONET operations, refer to the Bellcore SONET standard document.
Figure 2. SONET Structure
Functions
Payload to SPE mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Path layer Line layer Section layer
Path layer Line layer Section layer
Photonic layer
Photonic layer
End Equipment
Fiber Cable End Equipment
Table 1. SONET Signal Hierarchy
Elec.
STS-1 STS-3 STS-12 STS-24 STS-48
CCITT
STM-1 STM-4 STM-8 STM-16
Optical Data Rate (Mbps)
OC-1 OC-3 OC-12 OC-24 OC-48 51.84 155.52 622.08 1244.16 2488.32
Figure 3. STS-48/OC-48 Frame Format
A1 A1 9 Rows A1 A1 48 A1 Bytes A2 A2 A2 A2 48 A2 Bytes
Transport Overhead 144 Columns 144 x 9 = 1296 bytes v
Synchronous Payload Envelope 4176 Columns 4176 x 9 = 37,584 bytes v
125 sec
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER S3043 OVERVIEW
The S3043 transmitter implements SONET/SDH serialization and transmission functions. The block diagram in Figure 4 shows the basic operation of the chip. This chip can be used to implement the front end of SONET equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip includes parallel-to-serial conversion and system timing. The system timing circuitry consists of a high-speed phase detector, clock dividers, and clock distribution throughout the front end. The sequence of operations is as follows:
S3043
Transmitter Operations: 1. 16-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Internal clocking and control functions are transparent to the user. Details of data timing can be seen in Figures 7, 16 and 17. Suggested Interface Devices
AMCC S3040 OC-48 Clock Recovery Device AMCC S3044 OC-48 Receiver
Figure 4. S3043 Functional Block Diagram
DLEB LLDP/N LLCLKP/N LLEB LSDP/N PIN[15:0] PICLKP/N 16 FIFO 16:1 PARALLEL TO SERIAL M U X D TSDP/N
LSCLKP/N M U X TSCLKP/N PCLKP/N
TIMING GEN READ PULSE
TESTEN CLOCK DIVIDER and PHASE DETECTOR REFCLKP/N RSTB CAP1/2 2
LOCKDET
155MCK
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S3043 S3043 ARCHITECTURE/FUNCTIONAL DESIGN
MUX OPERATION
The S3043 performs the serializing stage in the processing of a transmit SONET STS-48 bit serial data stream. It converts the byte serial 155.52 Mbyte/sec data stream to bit serial format at 2.488 Gbps. Diagnostic loopback is provided (transmitter to receiver), and Line Loopback is also provided (receiver to transmitter). A high-frequency bit clock is generated from a 155.52 MHz frequency reference by using a frequency synthesizer consisting of an on-chip phaselocked loop circuit with a divider, VCO and loop filter. Clock Divider and Phase Detector The clock divider and phase detector, shown in the block diagram in Figure 4, contains monolithic PLL components that generate signals required to drive the loop filter. The REFCLK input must be generated from a differential LVPECL crystal oscillator which has a frequency accuracy of better than 20 ppm in order for the VCOCLK frequency to have the same accuracy required for operation in a SONET system. In order to meet the 0.01 UI SONET jitter specifications, the maximum reference clock jitter must be guaranteed over the 12 kHz to 20 MHz bandwidth. For details of reference clock jitter requirements, see Table 2. The on-chip phase detector, which compares the phase relationship between the VCO input and the REFCLK input, drives the loop filter. Timing Generator The timing generator function, seen in Figure 4, provides two separate functions. It provides a byte rate version of the TSCLK, and a mechanism for aligning the phase between the incoming byte clock and the clock which loads the parallel-to-serial shift register.
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
The PCLK output is a byte rate version of TSCLK. For STS-48, the PCLK frequency is 155.52 MHz. PCLK is intended for use as a byte speed clock for upstream multiplexing and overhead processing circuits. Using PCLK for upstream circuits will ensure a stable frequency and phase relationship between the data coming into and leaving the S3043 device. In the parallel-to-serial conversion process, the incoming data is passed from the PICLK byte clock timing domain to the internally generated byte clock timing domain, which is phase aligned to TSCLK. The timing generator also produces a feedback reference clock to the Phase Detector. A counter divides the synthesized clock down to the same frequency as the reference clock REFCLK. Parallel-to-Serial Converter The parallel-to-serial converter shown in Figure 4 is comprised of two byte-wide registers. The first register latches the data from the PIN[15:0] bus on the rising edge of PICLK. The second register is a parallel loadable shift register which takes its parallel input from the first register. An internally generated byte clock, which is phase aligned to the transmit serial clock as described in the Timing Generator description, activates the parallel data transfer between registers. The serial data is shifted out of the second register at the TSCLK rate.
OTHER OPERATING MODES
Diagnostic Loopback When the Diagnostic Loopback Enable (DLEB) input is low, a loopback from the transmitter to the receiver at the serial data rate can be set up for diagnostic purposes. The differential serial output data from the transmitter is routed to the receiver in place of the normal data stream (RSD). Line Loopback The line loopback circuitry consists of alternate clock and data output drivers. For the S3043, it selects the source of the data and clock which is output on TSD and TSCLK. When the Line Loopback Enable (LLEB) input is active, it selects data and clock from the Parallel to Serial Converter block. When LLEB is inactive, it forces the output data multiplexer to select data and clock from the LLD and LLCLK inputs, and a receive-to-transmit loopback can be established at the serial data rate.
Table 2. Reference Jitter Limits
Maximum Reference Clock Jitter in 12 kHz to 20 MHz Band 1 ps rms Operating Mode STS-48
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 3. Input Pin Assignment and Descriptions
Pin Name PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15 PICLKP PICLKN Level SingleEnded LVPECL I/O I Pin # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 22 21 Description
S3043
Parallel Data Input. A 155.52 Mbyte/sec word, aligned to the PICLK parallel input clock. PIN[15] is the most significant bit (corresponding to bit 1 of each PCM word, the first bit transmitted). PIN[0] is the least significant bit (corresponding to bit 16 of each PCM word, the last bit transmitted). PIN[15:0] is sampled on the rising edge of PICLK.
Diff. LVPECL
I
Parallel Input Clock. A 155.52 MHz nominally 50% duty cycle input clock, to which PIN[15:0] is aligned. PICLK is used to transfer the data on the PIN inputs into a holding register in the parallel-to-serial converter. The rising edge of PICLK samples PIN[15:0]. Line Loopback Data. Inputs normally provided from a companion S3044 device. Used to implement a line loopback function in which the receive serial bit serial data and clock signals are regenerated and passed through the S3043 transmitter. Internally terminated. Line Loopback Clock. Inputs normally provided from a companion S3044 device. Used to implement a line loopback function in which the receive serial bit serial data and clock signals are regenerated and passed through the S3043 transmitter. Internally terminated. Test Clock Enable. Set High to provide access to the PLL during production tests. Reference Clock. Input used as the reference for the internal bit clock frequency synthesizer. Internally terminated and biased.
LLDP LLDN
Externally Biased Diff. LVPECL Externally Biased Diff. LVPECL LVTTL Internally Biased Diff. LVPECL LVTTL
I
14 15
LLCLKP LLCLKN
I
11 12
TESTEN REFCLKP REFCLKN
I I
13 78 77
DLEB
I
8
Diagnostic Loopback Enable. Active Low. When active, selects diagnostic loopback. When DLEB is inactive, LSD and LSCLK are powered down and inactive. When active, the diagnostic loopback clock, (LSCLK), and data (LSD) outputs are active. TSD and TSCLK remain active in both states of DLEB. Master Reset. Reset input for the device, active Low. During reset, PCLK does not toggle.
RSTB
LVTTL
I
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S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 3. Input Pin Assignment and Descriptions (Continued)
Pin Name LLEB Level LVTTL I/O I Pin # 5 Description Line Loopback Enable. Selects Line Loopback. Active Low. When LLEB is active, the S3043 will route the data from the LLD/LLCLK inputs to the TSD/TSCLK outputs. Loop Filter Pins. Connections for external loop filter capacitor and resistors. Elastic Store Write Single-Ended Input. This input pin is clocked in using the rising edge of PICLK clock. This input is used to align the elastic store. The S3043 MUX will monitor the READ input for a fault condition.
CAP1 CAP2 READ
Analog SingleEnded LVPECL
I I
67 66 45
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SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 4. Output Pin Assignment and Descriptions
Pin Name TSCLKP TSCLKN TSDP TSDN PCLKP PCLKN LSDP LSDN Level Diff. CML Diff. CML Diff. LVPECL Low Swing Diff. CML Low Swing Diff. CML SingleEnded LVPECL SingleEnded LVPECL I/O O O O Pin # 57 56 55 54 23 24 6 7 Description
S3043
Transmit Clock Output. Transmit serial clock output that can be used to retime the TSD signal. Transmit Serial Data. Serial data stream signals, normally connected to an optical transmitter module. Parallel Clock. A reference clock generated by dividing the internal bit clock by sixteen. It is normally used to coordinate byte-wide transfers between upstream logic and the S3043 device. Loopback Serial Data. Serial data stream signals normally connected to a companion S3044 device for diagnostic loopback purposes. The LSD outputs are updated on the falling edge of the LSCLK. Loopback Serial Clock. Serial clock signals normally connected to a companion S3044 device for diagnostic loopback purposes. The LSD outputs are updated on the falling edge of the LSCLK. 155 MHz Clock Output. 155 MHz clock output from the clock synthesizer. This output should be connected to the reference clock input of the external clock recovery function (such as the S3040). Elastic Store Read Single-Ended Outputs. This output pulse is sychronized with the falling edge of PCLKP/N. This signal is used to align the elastic store. The PULSE output should be active for only one pulse every third 155 MHz clock cycle during the normal (no fault) operation. Lock Detect. Goes Low after the PLL has locked to the clock provided on the REFCLK pins. LOCKDET is an asynchronous output.
O
LSCLKP LSCLKN 155MCK
O
1 2 20
O
PULSE
O
43
LOCKDET
LVTTL
O
47
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S3043
Table 5. Common Pin Assignment and Description
Pin Name COREGND COREVCC LVPECLVCC LVPECLGND TTLVCC LVTTLGND NC LVPECLVCC LVPECLGND AVCC AGND +3.3V GND +3.3V GND Level GND +3.3V +3.3V GND +3.3V GND I/O Pin #
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Description
51, 61, Core Ground 63, 65, 75 50, 60, Core VCC 62, 64, 70 3, 16, 17, 52, 59 4, 10, 18, 53, 58 48 19 44, 46, 49, 76 41 42 69, 72, 74, 80 68, 71 73, 79 LVPECL VCC LVPECL Ground TTL VC C TTL Ground Not Connected LVPECL VCC LVPECL Ground Analog VCC Analog Ground
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Figure 5. S3043 Pinout
S3043
LSCLKP LSCLKN LVPECLVCC LVPECLGND LLEB LSDP LSDN DLEB RSTB LVPECLGND LLCLKP LLCLKN TESTEN LLDP LLDN LVPECLVCC LVPECLVCC LVPECLGND LVTTLGND 155MCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AVCC AGND REFCLKP REFCLKN NC COREGND AVCC AGND AVCC AGND COREVCC AVCC AGND CAP1 CAP2 COREGND COREVCC COREGND COREVCC COREGND
S3043 80 PQFP/TEP TOP VIEW
COREVCC LVPECLVCC LVPECLGND TSCLKP TSCLKN TSDP TSDN LVPECLGND LVPECLVCC COREGND COREVCC NC TTLVCC LOCKDET NC READ NC PULSE LVPECLGND LVPECLVCC
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PICLKN PICLKP PCLKP PCLKN PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
9
S3043
Figure 6. 80 PQFP/TEP Package
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
BOTTOM VIEW TOP VIEW
Note: The S3043 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and vias should not appear in the area immediately under the package. This heatsink is electrically biased to the Vee potential of the S3043. For optimum thermal management, a foil surface at ground (or Vee if other than ground) is recommended immediately under the package, and connected with multiple vias to the internal plane(s) of similar potential. Thermally conductive epoxy or other conductive interposer can be used to establish a good thermal dissipation path.
Table 6. Thermal Management
Device S3043
1. Add 0.24 W for loopback active.
Max 1.56 W
jc 2.1C/W
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Table 7. Performance Specifications
Parameter Nominal VCO Center Frequency TSCLK Clock Output Jitter OC-48/STS-48 Data Output Jitter STS-48 155.52 MHz Ref. Clk. Reference Clock Frequency Tolerance Reference Clock Input Duty Cycle Reference Clock Rise & Fall Times -100 30 Min Typ 2.488 12% Max Units GHz Conditions
S3043
0.01
UI (rms)
0.01 +100 70 1.5
UI (rms) ppm % ns
rms jitter, in lock. 20 ppm. Required to meet SONET output frequency specification.
20% to 80% of amplitude.
Table 8. Absolute Maximum Ratings
Parameter Storage Temperature Voltage on VCC with Respect to GND Voltage on any LVTTL Input Pin Voltage on any LVPECL Input Pin LVTTL Output Sink Current LVTTL Output Source Current High Speed LVPECL Output Source Current Static Discharge Voltage1
1. Except CAP1, CAP2.
Min -65 -0.5 -0.5 0
Typ
Max 150 +5.0 +5.5 VCC 8 8 50
Units C V V V mA mA mA V
500
Table 9. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on VCC with Respect to GND Voltage on any LVPECL Input Pin 3.135 VCC -2 3.3 Min -40 Typ Max 85 130 3.465 VCC Units C C V V
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S3043
Table 10. Power Consumption
Parameter ICC1
1. Add 70 mA for loopback active.
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Min
Typ 383
Max 450
Units mA
Table 11. LVTTL Input/Output DC Characteristics
Symbol VIH VIL IIH IIL VOH Description Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Conditions TTL VCC = Max TTL VCC = Max VIN = 2.4 V VIN = 0.5 V VIH = Min. VIL = Max. IOH = -100 A VIH = Min. VIL = Max. IoL = 4 mA -500 2.1 Min 2.0 0.0 Typ Max TTL VCC + 1.0 0.8 50 Unit V V A A V
VOL
Output Low Voltage
0.5
V
Table 12. Differential CML Output DC Characteristics
Parameter VOL VOH VOUTDIFF VOUTSINGLE Description CML Output LOW Voltage CML Output HIGH Voltage CML Serial Output Differential Voltage Swing CML Serial Output Singleended Voltage Swing Min Vcc -0.95 Vcc -0.35 560 280 Typ Max Vcc -0.55 Vcc -0.10 1300 650 Units V V mV mV Condition 100 line-to-line. 100 line-to-line. 100 line-to-line. See Figure 18. 100 line-to-line. See Figure 18.
Table 13. Low Swing Differential CML Output DC Characteristics
Parameters VOL VOH VOUTDIFF VOUTSINGLE Description Loopback CML Output LOW Voltage Loopback CML Output HIGH Voltage Loopback CML Serial Output Differential Voltage Swing Loopback CML Serial Output Single-ended Voltage Swing Min Vcc -0.50 Vcc -0.20 360 180 Typ Max Vcc -0.25 Vcc -0.05 800 400 Units V V mV mV Conditions 100 line-to-line. 100 line-to-line. 100 line-to-line. 100 line-to-line.
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Table 14. Internally Biased Differential LVPECL Input DC Characteristics
Parameters VBIAS VINDIFF VINSINGLE RDIFF Description LVPECL DC Bias Voltage Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Min Vcc -1.2 300 150 80 100 Typ Max Vcc -0.8 1200 600 120 Units V mV mV Conditions Inputs open. See Figure 18. See Figure 18.
S3043
Table 15. Externally Biased Differential LVPECL Input DC Characteristics
Parameters VIL VIH VINDIFF VINSINGLE RDIFF Description LVPECL Input LOW Voltage LVPECL Input HIGH Voltage Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Min Vcc -2.000 Vcc -1.20 300 150 80 100 Typ Max Vcc -0.25 Vcc -0.05 1200 600 120 Units V V mV mV See Figure 18. See Figure 18. Conditions
Table 16. Single Ended LVPECL Input DC Characteristics1
Parameters VIL VIH Description PECL Input Low Voltage PECL Input High Voltage Min Vcc -2.30 Vcc -1.250 Typ Max Vcc -1.441 Vcc -0.570 Units V V Conditions Guaranteed at 85 C. Guaranteed at 85 C.
1. The AMCC LVPECL inputs (VIL and VIH) are non-temperature compensated I/O which vary at 1.3mV/C.
Table 17. Single Ended LVPECL Output DC Characteristics1
Parameters VOL VOH Description PECL Output Low Voltage PECL Output High Voltage Min Vcc -2.2 Vcc -1.2 Typ Max Vcc -1.50 Vcc -0.65 Units V V Conditions
1. For 155MCK and Pulse signals. Maximum voltage swing = 500 mV for these two signals.
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S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Table 18. Differential LVPECL Input DC Characteristics
Parameters VIL VIH VINDIFF VINSINGLE Description LVPECL Input Low LVPECL Input High Diff. Input Voltage Swing Single Ended Input Voltage Swing Min Vcc -2.0 Vcc -1.2 400 20 0 Typ Max Vcc -0.5 Vcc -0.3 2000 1000 Units V V mV mV See Figure 18. See Figure 18. Comments
Table 19. Differential LVPECL Output DC Characteristics
Parameters VOUTSINGLE VOUTDIFF VOH VOL Description Single Ended Output Voltage Swing Diff. Output Voltage Swing Output High Voltage Output Low Voltage Min 550 1100 Vcc -1.15 Vcc -1.95 Typ Max 950 1900 Vcc -0.60 Vcc -1.50 Units mV mV V V Comments 220 to GND, 100 line to line. See Figure 12. 220 to GND, 100 line to line. See Figure 12. 220 to GND, 100 line to line. See Figure 12. 220 to GND, 100 line to line. See Figure 12.
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Figure 7. Line Loopback Input Timing Diagram
S3043
LLCLKP tSLLD LLDP/N
Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
tHLLD
Table 20. AC Transmitter Timing Characteristics
Symbol Description TSCLK/LSCLK Frequency (nom. 2.48 GHz) TSCLK/LSCLK Duty Cycle PICLK Duty Cycle t S PIN t H PIN t P TSD t S TSD t H TSD t S LLD t H LLD READ, PIN [15.0] Set-up Time w.r.t. PICLKP READ, PIN [15.0] Hold Time w.r.t. PICLKP TSCLK/LSCLK Low to TSD/LSD Valid Propagation Delay* TSD/LSD Set-up Time w.r.t. TSCLK/LSCLK TSD/LSD Hold Time w.r.t. TSCLK/LSCLK LLDP/N Set-up Time w.r.t. LLCLKP/N LLDP/N Hold Time w.r.t. LLCLKP/N PCLKP/N Duty Cycle CML Output Rise and Fall Time (20% - 80%) t P PICLK t P PRCLK t S PULSE t H PULSE t P REFCLK PICLK Delay from PCLK READ Delay from PULSE PULSE Set-up Time w.r.t. PCLK PULSE Hold Time w.r.t. PCLK PCLK Delay from REFCLK 0 0 1.8 2.0 6.5 40 40 1.5 0.5 -100 105 105 100 100 43 57 170 13 13 100 Min Max 2.6 60 60 Units GHz % % ns ns ps ps ps ps ps % ps ns ns ns ns ns
* Measured at 50/50 nominal duty cycle.
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S3043
Figure 8. External Loop Filter
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
2.2 F 75 CAP1 75 CAP2
Figure 9. CML Output to +5V PECL Input AC Coupled Termination
+3.3V
0.01 F
Zo=50 100
+5V
0.01 F S3043 TSDP/N TSCLKP/N
Zo=50
Figure 10. -5V Single Ended ECL Driver to S3043 Input AC Coupled Termination
-5.2V 0.01 F 330 -5.2V
+3.3V 82 Zo=50 130
+3.3V
ECL
S3043
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Figure 11. +5V Differential PECL Driver to S3043 Input AC Coupled Termination
S3043
+5V 0.01F Zo=50 330
3.3V 82 3.3V 130 82 0.01F Zo=50 130
+3.3V
330
S3043 PICLKP/N
Figure 12. S3043 to S3043 Terminations
+3.3V Zo=50 220 220 Zo=50 S3043 PCLKP/N S3043 PICLKP/N 100
+3.3V
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S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 13. Single-Ended PECL Output Termination
+3.3V Zo=50 330
+3.3V
S3043 PULSE
S3043 READ
Figure 14. S3043 to S3044 for Diagnostic Loopback
+3.3 V 0.01 F Zo=50
3.3 V 1 k 3.3 V 1 k 6.2 k 100
+3.3 V
6.2 k 0.01 F Zo=50 S3043 LSDP/N LSCLKP/N
S3044 LSDP/N LSCLKP/N
Figure 15. Single-Ended LVPECL Driver to S3043 Input AC Coupled Termination
Vcc 0.01F Zo=50 300 0.01F
Vcc -0.70V (DC AVG)
+3.3V
60
Vcc -0.70V (DC AVG) Single-Ended Driver S3043 REFCLKP/N
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Figure 16. AC Input Timing
S3043
PICLKP
tS PIN tH PIN
PIN[15:0]
1. When a set-up time is specified on LVPECL signals between an input and a clock, the set-up time is the time in picoseconds from the 50% point of the input to the 50% point of the clock. 2. When a hold time is specified on LVPECL signals between an input and a clock, the hold time is the time in picoseconds from the 50% point of the clock to the 50% point of the input.
Figure 17. Output Timing
TSCLKP/ LSCLKP
tPTSD tSTSD tHTSD
TSD/ LSD
Notes on High-Speed PECL Output Timing 1. Output propagation delay time is the time in nanoseconds from thecross-over point of the reference signal to the cross-over point of the output. 2. When a set-up time is specified on differential LVPECL signals between an input and a clock, the set-up time is the time in picoseconds from the cross-over point of the input to the cross-over point of the clock. 3. When a hold time is specified on differential LVPECL signals between an input and a clock, the hold time is the time in picoseconds from the cross-over point of the clock to the cross-over point of the input.
Figure 18. Differential Voltage Measurement
Single-ended swing
V SINGLE
V DIFF = 2X Single-ended swing
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APPLICATION NOTE
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
The S3043 utilizes a unique elastic store buffer which can be set in two different configurations allowing the system designer to be flexible in the way a system is to be layed out. The configuration of the elastic store buffer is dependent upon the I/O pins which comprise the Synch Timing loop. This loop is formed from PULSE(I/P) to READ(O/P) and PCLK(I/P) to PICLK(O/P). The elastic store buffer can be thought of as a memory stack with a read pointer. The PULSE signal is the read pointer which announces that it has read a register and when fed back to READ input, it synchronizes the write operation of the buffer so as not to simultaneously write over the same register that it has read previously.
Figure 19. Block Diagram
OSCILLATOR
REFCLK P/N
PCLK P/N PICLK P/N
DIV
PLL
16
PIN[15:0] FIFO
Pulse
Read
CUSTOMER LOGIC
S3043
Block Diagram
In the configuration shown above, both the loops (PCLK to PICLK) and (Pulse to Read) have 0 delay (they are shorted). S3043 is clocking data out of the customer logic. The oscillator frequency REFCLK is given to the PLL. The output of the PLL is given to the multiplier and divider circuits. The output of the chip PCLK, is used to clock data out of the customer logic. The PICLK is in phase and has the same frequency as PCLK. It is used to clock data into the register in the S3043. The data will have the same frequency as PICLK, but it may not be in phase with PICLK. It is important to meet the set-up and hold time constraints in this case.
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December 8, 2000 / Revision G
APPLICATION NOTE
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 20.
S3043
PCLK
PICLK
tHPIN tSPIN
PIN[15:0]
VALID DATA 1
VALID DATA 2
VALID DATA 3
VALID DATA 4
tSPIN
tHPIN
PULSE
READ
DON'T CARE
December 8, 2000 / Revision G
21
APPLICATION NOTE
S3043
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
In the figure shown below, we are using the 2nd configuration of the elastic store buffer. This configuration fully utilizes the elastic store buffer and allows the user a delay accommodation of 0 to 14 ns. The PULSE delay must follow the PCLK delay. It is very important that the relationship between these two signals be kept all the way through the loop. Otherwise it is possible to under or over spill the buffer. It is important to insure that the PULSE signal is retimed along with the outgoing data to the S3043.
Figure 21.
OSCILLATOR
REFCLK P/N
PCLK P/N PICLK P/N
DIV
PLL
16
PIN[15:0] FIFO
D Q CUSTOMER LOGIC
Pulse Read S3043
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December 8, 2000 / Revision G
APPLICATION NOTE
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Figure 22.
S3043
PCLK
tPPICLK
PICLK
tSPULSE tHPULSE
PULSE tPPRCLK tHPIN
READ
tSPIN
tHPIN tSPIN PIN[15:0]
VALID DATA 1
VALID DATA 2
VALID DATA 3
December 8, 2000 / Revision G
23
APPLICATION NOTE
S3043
Figure 23.
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
OSCILLATOR
REFCLK P/N
DIV
PICLK P/N
PLL
16
PIN[15:0] FIFO
Pulse
Read
CUSTOMER LOGIC
S3043
In some applications it is necessary to "forward clock" the data in a SONET/SDH system. In this application the reference clock from which the high speed serial clock is synthesized and the parallel data clock both originate from the same clock source. The timing control logic in the S3043 automatically generates an internal load signal which has the fixed relationship to the reference clock. The logic takes into account the variation of the reference clock to the internal load signal over temperature and voltage. The connections required to implement the design are shown in the above figure. The setup and hold times for the PICLK to the data must be met by the customer logic. For the timing diagram refer to Figure 16. Possible Problems: In order to meet the jitter generation specifications required by SONET, the jitter of the reference clock must be minimized. It may be difficult to meet the SONET jitter generation specifications using a reference clock generated from the customer logic.
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December 8, 2000 / Revision G
SONET/SDH/ATM OC-48 16:1 TRANSMITTER
Ordering Information
GRADE TRANSMITTER PACKAGE
S3043
S - Industrial/Commercial
3043
A - 80 PQFP/TEP
X
XXXX
X
Package
Grade Part number
IS
O 90 0
RT
IFI
Applied Micro Circuits Corporation 6290 Sequence Drive, San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 2000 Applied Micro Circuits Corporation D204/R333
December 8, 2000 / Revision G
E
D
1
CE
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